10-1 phase:basic UVM测试平台层次结构与Phase执行顺序解析

原始代码及log

module top;import uvm_pkg::*;//Create a topology// top// | |// u1(A) u2(A)// | | | |// b1(B) d1(D) b1(B) d1(D)//No run phaseclassDextends uvm_component;functionnew(string name,uvm_component parent);super.new(name,parent);endfunction functionvoidbuild_phase(uvm_phase phase);$display("%0t: %0s: build",$time,get_full_name());endfunction functionvoidend_of_elaboration_phase(uvm_phase phase);$display("%0t: %0s: end_of_elaboration",$time,get_full_name());endfunction functionvoidstart_of_simulation_phase(uvm_phase phase);$display("%0t: %0s: start_of_simulation",$time,get_full_name());endfunction functionvoidextract_phase(uvm_phase phase);$display("%0t: %0s: extract",$time,get_full_name());endfunction functionvoidcheck_phase(uvm_phase phase);$display("%0t: %0s: check",$time,get_full_name());endfunction functionvoidreport_phase(uvm_phase phase);$display("%0t: %0s: report",$time,get_full_name());endfunction endclass//Has run phaseclassBextends uvm_component;rand logic[7:0]delay;functionnew(string name,uvm_component parent);super.new(name,parent);endfunction functionvoidbuild_phase(uvm_phase phase);$display("%0t: %0s: build",$time,get_full_name());endfunction functionvoidend_of_elaboration_phase(uvm_phase phase);$display("%0t: %0s: end_of_elaboration",$time,get_full_name());endfunction functionvoidstart_of_simulation_phase(uvm_phase phase);$display("%0t: %0s: start_of_simulation",$time,get_full_name());endfunction functionvoidextract_phase(uvm_phase phase);$display("%0t: %0s: extract",$time,get_full_name());endfunction functionvoidcheck_phase(uvm_phase phase);$display("%0t: %0s: check",$time,get_full_name());endfunction functionvoidreport_phase(uvm_phase phase);$display("%0t: %0s: report",$time,get_full_name());endfunction taskrun_phase(uvm_phase phase);$display("%0t: %0s: start run phase",$time,get_full_name());#delay;$display("%0t: %0s: end run phase",$time,get_full_name(