ResetVector
查阅处理器相关规范，了解到x86架构的计算机上电或者重启后，会跳转到0xFFFFFFF0(Reset Vector)处执行指令，OVMF平台reset vector代码（OvmfPkg\ResetVector\Ia16\ResetVectorVtf0.asm）如下：
resetVector: ; ; Reset Vector ; ; This is where the processor will begin execution ; ; In IA32 we follow the standard reset vector flow. While in X64, Td guest ; may be supported. Td guest requires the startup mode to be 32-bit ; protected mode but the legacy VM startup mode is 16-bit real mode. ; To make NASM generate such shared entry code that behaves correctly in ; both 16-bit and 32-bit mode, more BITS directives are added. ; %ifdef ARCH_IA32 nop nop jmp EarlyBspInitReal16- NOP：根据SDM手册，对于多核处理器。第一个执行NOP指令的核，被设置为BSP，负责执行指令。第二个NOP负责占位，保证16位对齐。
ResetVector.bin
查阅ResetVector.inf module经编译后的二进制文件ResetVector.bin（Build\Ovmf3264\NOOPT_VS2019\IA32\OvmfPkg\ResetVector\ResetVector\OUTPUT\ResetVector.bin），我们可以看到。上述代码对应的机器指令是90 90 E9 5B FF。
ResetVector.lst
EDK2在编译ResetVector.inf的时候，会将其先翻译成ResetVector.lst（Build\Ovmf3264\NOOPT_VS2019\IA32\OvmfPkg\ResetVector\ResetVector\OUTPUT\ResetVector.lst），我们可以比较方便查阅上述代码编译后的机器码，如下：
179<1>resetVector:180<1>;181<1>;Reset Vector182<1>;183<1>;This is where the processor will begin execution184<1>;185<1>;In IA32 we follow the standard reset vector flow. WhileinX64, Td guest186<1>;may be supported. Td guest requires the startup mode to be32-bit187<1>;protected mode but the legacy VM startup mode is16-bit real mode.188<1>;TomakeNASM generate such shared entry code that behaves correctlyin189<1>;both16-bit and32-bit mode,moreBITS directives are added.190<1>;191<1>%ifdef ARCH_IA321920000056090<1>nop1930000056190<1>nop19400000562 E95BFF<1>jmp EarlyBspInitReal16通过WinDbg查询内存地址0xFFFFFFF0位置的指令，可以看到和上述一致：
参考
Intel SDM
Upon completion of the BIST, the logical processors use a hardware-defined selection mechanism toselectthe BSP and the APs from the available logical processors on the system bus. The BSP selection mechanism differs depending on the family, model, and stepping IDs of the processors, as follows: — Later generations of IA processors within family 0FH(see Section9.4), IA processors with system bus(family=06H,extended_model=0, model>=0EH), or all other modern Intel processors(family=06H, extended_model>0): • The logical processors begin monitoring the BNR# signal, which is toggling. When the BNR# pin stopstoggling, each processor attempts to issue a NOP special cycle on the system bus. • The logical processor with the highest arbitration priority succeedsinissuing a NOP special cycle and is nominated the BSP. This processor sets the BSP flaginits IA32_APIC_BASE MSR,thenfetches and begins executing BIOS boot-strap code, beginning at the reset vector(physical address FFFF FFF0H). • The remaining logical processors(that failedinissuing a NOP special cycle)are designated as APs. They leave their BSP flagsintheclearstate and enter a “wait-for-SIPI state.”OVMF_ResetVector
